Cypress Semiconductor /psoc63 /BLE /RCB /INTR_SET

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Interpret as INTR_SET

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RCB_DONE)RCB_DONE 0 (TX_FIFO_TRIGGER)TX_FIFO_TRIGGER 0 (TX_FIFO_NOT_FULL)TX_FIFO_NOT_FULL 0 (TX_FIFO_EMPTY)TX_FIFO_EMPTY 0 (TX_FIFO_OVERFLOW)TX_FIFO_OVERFLOW 0 (TX_FIFO_UNDERFLOW)TX_FIFO_UNDERFLOW 0 (RX_FIFO_TRIGGER)RX_FIFO_TRIGGER 0 (RX_FIFO_NOT_EMPTY)RX_FIFO_NOT_EMPTY 0 (RX_FIFO_FULL)RX_FIFO_FULL 0 (RX_FIFO_OVERFLOW)RX_FIFO_OVERFLOW 0 (RX_FIFO_UNDERFLOW)RX_FIFO_UNDERFLOW

Description

Master interrupt set request register

Fields

RCB_DONE

Write with ‘1’ to set corresponding bit in interrupt request register.

TX_FIFO_TRIGGER

Write with ‘1’ to set corresponding bit in interrupt request register.

TX_FIFO_NOT_FULL

Write with ‘1’ to set corresponding bit in interrupt request register.

TX_FIFO_EMPTY

Write with ‘1’ to set corresponding bit in interrupt request register.

TX_FIFO_OVERFLOW

Write with ‘1’ to set corresponding bit in interrupt request register.

TX_FIFO_UNDERFLOW

Write with ‘1’ to set corresponding bit in interrupt request register.

RX_FIFO_TRIGGER

Write with ‘1’ to set corresponding bit in interrupt request register.

RX_FIFO_NOT_EMPTY

Write with ‘1’ to set corresponding bit in interrupt request register.

RX_FIFO_FULL

Write with ‘1’ to set corresponding bit in interrupt request register.

RX_FIFO_OVERFLOW

Write with ‘1’ to set corresponding bit in interrupt request register.

RX_FIFO_UNDERFLOW

Write with ‘1’ to set corresponding bit in interrupt request register.

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